Many integrated circuits (ICs) comprise a self-test circuit known as a Built-In Self-Test (BIST) circuit to test the integrated circuit. Logic BIST is used to electrically test the logic gates within the integrated circuit. For example, a BIST circuit generally includes a pattern generator for producing test patterns such that patterns are applied to the IC under test and the response thereto analyzed by means of a signature register output.
However, when embedded memories are present in the IC, one or more memory BIST controllers are generally required to test the embedded memory. Thus, the presence of memory BIST controllers generally results in substantial die area being consumed by the memory BIST controllers. Additionally, memory BIST controllers can introduce unacceptable timing delays in the input path of the embedded memory and generally require additional cost to develop and implement.